Topic profile page for FPGA.
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Topic "Fpga" was discussed 0 times on 0 sites in last 3 months
Started 4 days, 19 hours ago (2010-01-01 04:27:00)
by GaryMcT
Happy New Year everyone! What's been going on around here? Haven't been around much lately. Started messing around with FPGA programming at home with the goal to hopefully work on helping to get more games running accurately. Who knows if I'll get anywhere with it. The Pac-Man example here is very nice: http://www.fpgaarcade.com/games.htm Also, my wife surprised me with a gp2x ...
Started 1 week ago (2009-12-29 09:03:00)
by MiroslavS
Hello! I have an error and I don't now how to fix it...the error is Block Diagram Errors: Close FPGA VI Reference: target support for selected FPGA device is not installed Details: Install the correct support files I have already installed all CDs from NI (FPGA,RIO,Real...) I will be glad for every help...thanks by
Started 1 week, 1 day ago (2009-12-28 20:45:00)
by zeta
I'm taking a look at implementing this using verilog and some custom hardware equipped with several ethernet ports, doing historical data processing on FPGA, leaving remaining flops on the CPU. Thoughts?
Started 1 week, 5 days ago (2009-12-24 10:37:00)
by vgravel
Hello all, Here is my problem: When I'm running a FPGA VI using Teststand, it runs much slower than if I run it using only LabVIEW. My VI is doing digital acquisiton (32 bits at 5MHz) and sending the data via a DMA FIFO. My host VI read de DMA FIFO and log the data on the hard drive. If I run the VI directly in LabVIEW everything works fine and my DMA FIFO never become ...
Started 2 weeks, 1 day ago (2009-12-21 22:14:00)
by ayeckley
I'm having some issues with the 4X encoder setting. At one point circa February 09 (after the release of update 3a) there was a known bug in the FPGA code related to the 4X setting. Even after searching through CD, NI Communities, etc. I haven't been able to figure out if a fix was ever implemented. Can anyone (Greg?) confirm that FPGA 1.0.0 (which appears to be the image that accompanies ...
Started 2 weeks, 5 days ago (2009-12-17 03:42:00)
by prashiit
In a project, VIs are in different levels........... one is under My computer, one is under RT Target and one is under FPGA Target. Can we have a global variable among these VIs........................... Thanks Prashanth
Started 2 weeks, 6 days ago (2009-12-16 23:58:00)
by prashiit
Hello I have developed an application for processing a 2D array on FPGA. I am sending some of data at a time through DMA FIFOs to FPGA VI. But, When I run host VI(under RT target), FPGA VI is not running (under FPGA target). Should I manually run FPGA VI also........? Please reply.. Thanks Prashanth
Started 6 days, 6 hours ago (2009-12-30 18:05:00)
by DSPGuy
Are there any companies making very custom hardware for the financial field? Something along the lines of a computer specially designed for low latency (and I'm not talking about cobbling together a few off the shelf boards). Or perhaps a computer designed to solve a particular class of equations.
Started 3 days, 2 hours ago (2010-01-02 21:59:00)
by bojan
I know that some of the well-known derivatives dealers had proof-of-concept and pilot projects with FPGAs but never heard it going beyond that. Unfortunately I do not know precisely why they didn't make it beyond the pilot.
Started 1 week ago (2009-12-29 19:30:00)
by Tim C.
I have a CRIO 9012 I will be be doing very basic voltage, mv, and thermal couple readings. Data rate of once per second is to read the input is fine. Modules being used - 9221, 9215, 9211 Also using a GPIB-RS232 converter via the com1 on teh CRIO, this is being used to adjust DC load modules in an Agilent N3300A DC Load Bank. Test Plan FPGA gets AIs, ...
Started 6 days, 20 hours ago (2009-12-30 03:37:00)
by anquegi
Hi I have fedora 12 64 bits When I try to install the cd Altera complete design suite version 7.2 for UNIX and Linux, which comes with the cyclone II starter development kit, First I copy the cd to the my home directory and then run the installation and after the setting I get this error: -------------------------------------------------- ---------- Calculating disk space ...
Started 1 week ago (2009-12-29 09:09:00)
by dav383838
I have a cRIO 9073, Labview 2009 and a Ni 9401 DIO module. I don't have the Labview FPGA option and therefore using the scan engine. I need to ouput a fixed number of digital pulses at 350 hz and have access to at least 2 other digital lines. If I try generate the pulses using a loop and writing to the port, the highest rate that I can get is 50hz. If I try to use PWM (...
Started 1 day, 13 hours ago (2010-01-04 10:38:00)
by bela6423
Hi , During my project I have been building a data logger with a cRIO-9014 . The FPGA samples 11 input signals at the rate of 640 Hz , ie 7040 data point per second and continously writes to a DMA FIFO . On the RT Target I got two timed loops , one for reading the FIFO ( high ...
Started 1 week ago (2009-12-29 13:35:00)
by faycel.k
I am trying to compile stand-alone applications to run on the openSPARC on FPGA. According to the design and verification guide, i need to set up the following path: % setenv QTOOLS $SAM_ROOT/hypervisor/src/hypervisor-tools However, I cannot find where this directory is located. Can anyone point me in the right direction. please? Also, I will be compiling my applications using the...
Started 1 day, 15 hours ago (2010-01-04 09:00:00)
by Dev Hardware
In the following articles I will show you what an FPGA (Field Programmable Gate Array) is and how to program FPGAs. We will also create a little project that will show you a good example of what you can achieve with the help of these devices. Still, I will keep it as simple as possible to ease your understanding. Read the full article here: Field Programmable Gate Arrays: a Brief ...
Started 2 days, 13 hours ago (2010-01-03 10:24:00)
by outrun
Zeta (and others) This is my 2 cents: I think your target audience -those that need extremely low latency solutions- have in general algorithms that work like this: * inspect an incoming message, see if it matches some condition * if the condition is matched, then send out an order the condition can be lost of stuff: * the difference between two prices * the implied ...
